Senior FPGA Design Engineer

The Senior FPGA Design Engineer will be responsible for high reliable real-time FPGA logic development

BSc/ MSc in Electrical Engineering

-5 or more years of experience developing FPGA or ASIC systems.

-Experience in wireless communication/ Signal processing experience

-Proficient in Verilog RTL language. Experienced with large FPGA development on Xilinx or Intel devices.

– familiar with FPGA build flow including design entry in Verilog, synthesis, place and route, timing constraints and timing closure.

-Hands on experience with lab debug equipment, such as oscilloscopes and logic analyzers.

-Experience with verification methodologies, RTL and gate level simulations and debug.