Verification Engineer

The Verification Engineer will Join a multi-tasking dynamic team and will be In charge of planning (architecture) and developing (coding) all the needed simulation environments for tests and debugs

The function of this job requires the following major tasks:

Job requirements

• Assisting in the development of complex test environments for FPGA design.
• Assisting in conducting complex functional simulations during development stages.
• Assisting in developing test for automated environments and conducting verification testing.
• Proficient in the use of tools such as Verilog, system Verilog, UVM, FPGA, etc.

Job description

· BSC in Electrical Engineering/computer science.

· 2 years of experience with RTL verification.

· experience with system Verilog – an advantage.

· Knowledge in UVM – an advantage.

· Highly motivated and dynamic person.

· Team player.

· Fast learner.

· Able to work independently.